35 Repositories
Rust risc-v Libraries
Repo for apps for the Pocket RISC-V core for Analogue Pocket/OpenFPGA. Multiple branches.
This is a repo meant to host Rust programs for agg23's Pocket RISC-V platform. While Rust can be built out of the openfpga-litex repo directly, this r
A "Type 0" zkEVM. Prove validity of Ethereum blocks using RISC Zero's zkVM
zeth NEW: Zeth now supports Optimism blocks! Just pass in --network=optimism! Zeth is an open-source ZK block prover for Ethereum built on the RISC Ze
HAL for the CH58x family of microcontrollers. BLE 5.3, RISC-V Qingke V4.
ch58x-hal HAL for the CH58x RISC-V BLE microcotrollers from WCH. This crate is under random and active development. DO NOT USE in production. This sho
RISC-V instruction decoder written in Rust.
raki RISC-V instruction decoder written in Rust. Both 32/64bit support. Support rv32/64imac, Zicsr, Zifencei extensions. Implement Display trait for f
Assured Confidential Execution (ACE) for RISC-V
Assured Confidential Execution (ACE) for RISC-V ACE-RISCV is an open-source project, whose goal is to deliver a confidential computing framework with
A fast and secure RISC-V based virtual machine
PolkaVM PolkaVM is a general purpose user-level RISC-V based virtual machine. This project is still unfinished and is a very heavy work-in-progress! D
Risc-V hypervisor for TEE development
A micro hypervisor for RISC-V systems. Quick Start Building (using Bazel) git submodule update --init bazel build //:salus-all Running Prerequisites S
A RISC-V emulator written in Rust :crab:
R2 A RISC-V emulator written in Rust 🦀 . Inspired cnlohr/mini-rv32ima. Capture You can run linux in your browser. Playground https://bokuweb.github.i
An experimental RISC-V recompiler
WARNING: All of this code is highly experimental and is a direct result of a two day hacking binge fueled by a truckload of tea. It's definitely not s
An open source WCH-Link library/command line tool written in Rust.
wlink - WCH-Link command line tool NOTE: This tool is still in development and not ready for production use. Known Issue: Only support binary firmware
Simple RISC-V emulator presented at Rust Nation 2023
A tale of binary translation This repo contains the code for the RISC-V emulator that I presented at Rust Nation 2023. It is intended as a teaching ex
CosmWasm + zkVM RISC-V EFI template
cosmwasm-risc0-example CosmWasm + RISC-V zkVM gm example Overview CosmWasm RISC Zero This example exists to explore the patterns of use of CosmWasm an
Minimal runtime / startup for RISC-V CPUs from Espressif
esp-riscv-rt Minimal runtime / startup for RISC-V CPUs from Espressif. Much of the code in this repository originated in the rust-embedded/riscv-rt re
Following "ZK HACK III - Building On-chain Apps Off-chain Using RISC Zero"
RISC Zero Rust Starter Template Welcome to the RISC Zero Rust Starter Template! This template is intended to give you a starting point for building a
Risc-V assembly interpreter built with pure Rust
Risc-V Interpreter Interpreter for Risc-V assembly built with Rust Report bug · Request feature Table of contents Quick start Exemple Program Instruct
Parse RISC-V opcodes to provide more detailed structured data
riscv-opcodes-parser Parse RISC-V opcodes to provide more detailed structured data. License Licensed under either of Apache License, Version 2.0 (LICE
How to run Rust user programs on Xv6-RISC-V
Rust on Xv6-RISC-V How to run user Rust program in Xv6-RISC-V Run make init to add rist-v target to rustc Run make build to build the program. It will
Message Signaled Interrupts for RISC-V
RISC-V MSI Test in Rust Testing the new MSIs added by the draft Advanced Interrupt Architecture (AIA) specification. Blog Posts First blog post: 30-Ju
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
RISC Zero WARNING: This software is still experimental, we do not recommend it for production use (see Security section). RISC Zero is a zero-knowledg
rusty-riscy is a performance testing and system resource monitoring tool written in Rust to benchmark RISC-V processors.
rusty-riscy rusty-riscy is a performance testing and system resource monitoring tool written in Rust to benchmark RISC-V processors. Objectives To cre
A RISC-V emulator supoorting RV32I instruction set written in Rust
32-bit RISC-V Emulator in Rust This is a RISC-V emulator supoorting RV32I instruction set written in Rust, inspired by Francis Stokes's RISC-V Emulato
A RISC-V and unix-like operating system developed just for fun.
Orca 虎鲸 A RISC-V and unix-like operating system developed just for fun. Schedule [*] bootloader (use RustSBI-qemu) [ ] linker & stack [ ] memory alloc
CKB's vm, based on open source RISC-V ISA
Nervos CKB VM About CKB VM CKB VM is a pure software implementation of the RISC-V instruction set used as scripting VM in CKB. Right now it implements
RCore-Tutorial-v3 - Let's write an OS which can run on RISC-V in Rust from zero!
rCore-Tutorial-v3 rCore-Tutorial version 3.5. See the Documentation in Chinese. Official QQ group number: 735045051 news 2021.11.20: Now we are updati
An operating system kernel running on RISC-V arch. Developing...
An operating system kernel running on RISC-V arch How to build it Environmental requirement rustup ( =1.57.0-nightly) Qemu ( =5.0.0) Step Build loca
Cute tiny operating system for RISC-V. ฅ•ω•ฅ
MoeOS ⁄(⁄ ⁄•⁄ω⁄•⁄ ⁄)⁄ ٩(^ᴗ^)۶欢迎参观MoeOS的仓库,MoeOS是一个小巧可爱(并不)的操作系统,目前全力支持RISC-V中。 (*≧▽≦)因为还只是一个玩具操作系统,就别要求她能做太多事情啦!现在功能还不完善,会慢慢加的! 编译 呐,你想给我找个家么? 目前MoeOS
oreboot is a fork of coreboot, with C removed, written in Rust.
oreboot is a downstream fork of coreboot, i.e. oreboot is coreboot without 'c'.
Blink program on RISC L106 80Mhz 32bit CPU
esp8266-blink Blink program on RISC L106 80Mhz 32bit CPU Flashing Running rust on ESP* is sort of hard... We won't cover the installation process, ins
Rust library for emulating RISC-V rv32imac
This library can execute instructions against any memory and register file that implements the required primitives in the traits lib_rv32::traits::{Memory, RegisterFile}. This is to encourage usage with whatever frontend you desire.
Baremetal Backtracing on RISC-V
It provides a simple but useful backtrace in baremetal machine, basically it links DWARF info into the binary and print them when backtrace the program. Currently it only supports RISC-V architecture, but I did not see any barrier to make it available in other architectures like x86.
Low level access to T-Head Xuantie RISC-V processors
XuanTie Low level access to T-Head XuanTie RISC-V processors Contributing We welcome contribution! Please send an issue or pull request if you are rea
QEMU platform SBI support implementation, using RustSBI
QEMU support using RustSBI Compile and run with: cargo qemu When running cargo qemu, the test kernel will build and run. Expected output should be: xt
Trying embedded Rust on the Pinecil GD32VF103 RISC-V device.
Pinecil GD32VF103 RISC-V Rust Demos My personal collection of Rust demos running on the PINE64 Pinecil portable soldering iron, featuring a GD32VF103T
A secure embedded operating system for microcontrollers
Tock is an embedded operating system designed for running multiple concurrent, mutually distrustful applications on Cortex-M and RISC-V based embedded
A secure embedded operating system for microcontrollers
Tock is an embedded operating system designed for running multiple concurrent, mutually distrustful applications on Cortex-M and RISC-V based embedded