CKB's vm, based on open source RISC-V ISA

Overview

Nervos CKB VM

Build Status Build Status codecov


About CKB VM

CKB VM is a pure software implementation of the RISC-V instruction set used as scripting VM in CKB. Right now it implements full IMC instructions for both 32-bit and 64-bit register size support. In the future we might also implement V extensions to enable better crypto implementations.

License

Nervos CKB is released under the terms of the MIT license. See COPYING for more information or see https://opensource.org/licenses/MIT.

Development Process

This is now deployed and used in production CKB mainnet.

The develop branch is regularly built and tested, but is not guaranteed to be completely stable. CKB will use released versions of CKB VM which are tested and more stable.

The contribution workflow is described in CONTRIBUTING.md, and security policy is described in SECURITY.md. To propose new protocol or standard for Nervos, see Nervos RFC.


How to build

CKB VM is currently tested mainly with stable Rust version on 64-bit Linux, macOS, and Windows.

# download CKB VM
$ git clone https://github.com/nervosnetwork/ckb-vm
$ cd ckb-vm
$ cargo build

You can also run the tests:

make test

CKB VM has already included RISC-V binaries used in tests, so you don't need a RISC-V compiler to build binaries. However if you do want to play with your own binaries, a RISC-V compiler might be needed. riscv-tools can be a good starting point here, or if you are an expert on GNU toolchain, you might also compile upstream GCC from source with RISC-V support, here is an example. CKB VM is using standard RISC-V instructions and ELF binary format, so theoretically any RISC-V compatible compilers are able to produce contracts used in CKB VM(tho bug reports are very welcome if you find breakage).

Notes on Different Modes

Right now CKB VM has 3 different modes:

  • Rust interpreter mode
  • Assembly based interpreter mode(ASM mode)
  • Ahead-of-time compilation mode(AOT mode)

For consistent behavior, you should only use ASM or AOT mode, and it's best if you stick with either ASM or AOT mode depending on your use case. The Rust mode is developed more to assist development, and never used in production by us. In case of bugs, there might be inconsistent behaviors between Rust mode and ASM/AOT mode.

Comments
  • Use `reset()` as a general means to reuse machine

    Use `reset()` as a general means to reuse machine

    In the current CKB, a new machine needs to be created every time a script is executed, which means a malloc with a size of at least 4M. I consider using reset() to reset the state of the machine after each script execution is over, as shown below

    // Start execute first script
    machine.run()
    
    // Reset states of machine
    machine.reset()
    machine.set_max_cycles(_)
    machine.set_cycles(0)
    
    // Start execute next script
    machine.load_program(_)
    machin.run()
    

    But now there is a problem to think about: this approach breaks isolation.

    cc @driftluo

    opened by mohanson 11
  • B extension

    B extension

    Implement the B extension in the rust interpreter, asm machine and aot machine.

    Note that aot machine is not yet supported, also, there are two instructions not implemented on the asm machine: bmatxor and bmator.

    opened by mohanson 5
  • feat: Add new AOT mode to replace experimental JIT mode

    feat: Add new AOT mode to replace experimental JIT mode

    This PR adds a new AOT mode evolved from previously experimental JIT mode. It works by compiling a RISC-V program directly into x64 assemblies. After that, most of the code can just run in the compiled x64 assembly binary without any overhead.

    Benchmark shows that this can further bump VM performance from 6ms measured in assembly interpreter to ~1.5ms(of which ~0.9ms is the actual running time).

    With this new AOT mode, we are also removing our old JIT mode which serves its purpose.

    opened by xxuejie 5
  • Add coverage CI job containing full CKB VM test suite

    Add coverage CI job containing full CKB VM test suite

    This is adapted from #66 thanks to @u2's help!

    I originally rejected the idea of adding coverage job in #66 but upon further consideration, that's a mistake, we should add coverage job in this repo since:

    • Cross-posting coverage report from another repository is very tricky to get right
    • While test suite repo contains a lot of useful and complete tests, the tests included in this repo is a good supplement for invalid cases
    • With CI job here, bugs in PRs can be detected earlier
    opened by xxuejie 5
  • chore: add take api

    chore: add take api

    The snapshot only records the internal state(registers and memory) of the running VM. To fully restore the scene, we need to support all syscall、cycle calculation function and debugger function, rebuilding is too expensive each time, this PR will be added all take_* API to get the information inside the VM to facilitate the reconstruction

    opened by driftluo 4
  • feat: allow analysis elf before initialization vm

    feat: allow analysis elf before initialization vm

    Add a new package level function parse_elf() and a new method DefaultMachine.load_program_elf(&mut self, program: &Bytes, args: &[Bytes], elf: &Elf,), this allows analysis of the elf file before initializing the vm, while ensuring that it only needs to be parsed once.

    opened by mohanson 4
  • Introduce version and fix various bugs

    Introduce version and fix various bugs

    Since one major use case of CKB VM is on blockchains, we cannot just change the code in case of bugs. We have to wait for the next fork event, only then can we upgrade the code. Hence we are introducing a concept of versions in the VM, whenever we fix a bug that might alter behavior, we will insert checking code to only include the bug fix in the next VM version. This way blockchains can expect consistent VM behavior when they lock specific VM version.

    This PR also provides VM version 1 which fixes #92 #97 and #98

    opened by xxuejie 4
  • Stack pointer not aligned

    Stack pointer not aligned

    During stack initialization, as follows

    https://github.com/nervosnetwork/ckb-vm/blob/develop/src/machine/mod.rs#L159

    And as riscv-spec-v2.2.pdf, Page 77 says, "In the standard RISC-V calling convention, the stack pointer sp is always 16-byte aligned."

    inconsistent behavior here.

    opened by mohanson 4
  • test: add code coverage

    test: add code coverage

    https://github.com/nervosnetwork/ckb/pull/943

    Using kcov instead of tarpaulin, because it's for compiled programs not only Rust, and we can also compare with tarpaulin for a while.

    opened by u2 4
  • feat: Baseline JIT implementation

    feat: Baseline JIT implementation

    NOTE: this PR is quite huge but there are certain files(which contribute to more than half the changes here) we don't need to review:

    • Files in dynasm folder are pulled directly from official LuaJIT, there's no modification by us.
    • src/jit/asm.x64.compiled.c is translated from src/jit/asm.x64.c. Ideally, we might want to exclude this file and only generate it in build steps. But the problem is the translator here is written in Lua, and requires a real Lua binary to run it. As of now, there's no easy way to build a binary, then execute it in build.rs. Hence for simplicity reason, I just included src/jit/asm.x64.compiled.c here, in the future we might want to build a separate crate packaging Lua binary and dynasm translator here to handle this task.

    Closes #20

    opened by xxuejie 4
  • Compiled andi.c with 'riscv64-unknown-elf-gcc -o andi andi.c' not passing test

    Compiled andi.c with 'riscv64-unknown-elf-gcc -o andi andi.c' not passing test

    Greetings all!

    I'm trying to get the example programs that I compile myself to pass the tests, but it looks as though whatever I compile is not parsed correctly by the CKB VM. The provided binaries pass just fine. I've built the riscv toolchain as described here, and I've made no changes to the CKB-VM codebase. It appears as though my compiled andi and the provided version have the same symbols, although different sizes.

    Is there a compiler option I'm missing, or am I doing something silly I'm not seeing?

    Thanks for any help you're able to provide.

    s:triage 
    opened by TheRealBluesun 4
  • Enhance performance by changing trace cache strategy

    Enhance performance by changing trace cache strategy

    In ckb-vm, the algorithm in trace cache is like this:

    pub fn calculate_slot(addr: u64) -> usize {
        (addr as usize >> 5) & (8196-1)
    }
    

    We call 5 as shift amount below.

    The cache missing is very high for computation heavy code. Here is the statistics for bn128-example: https://github.com/cryptape/rvv-prototype/tree/ae405442b477a972e022016c2d791733c788cca7

    cd bn128-example
    make bench
    

    For different shift amount, we got the following data:

    when shift amount is 2:
    Use RVV:    0m3.444s
    Use IMC:    0m5.172s
    
    when shift amount is 3:
    Use RVV:    0m4.095s
    Use IMC:   0m5.081s
    
    when shift amount is 4:
    Use RVV:    0m4.958s
    Use IMC   0m5.798s
    
    when shift amount is 5:
    Use RVV:    0m6.084s
    Use IMC:    0m7.195s
    

    There are too many small trace fragments (< 8 instructions) in both RVV and IMC cases. It make cache missing very high. When shift amount is reduced to 2, every single instruction own one slot and the cache missing is dramatically reduced.

    opened by XuJiandong 1
  • Phase plan of the V instruction set

    Phase plan of the V instruction set

    Phase plan of the V instruction set

    The V instruction set has a large number of instructions, and it is difficult for us to complete these instructions at once, so these instructions are divided into 3 parts.

    • The first part needs to be implemented first
    • The second part depends on the situation
    • And the third part is instructions that we don’t need in the short term ( Floating / atomic instructions).

    Note: The first column: implemented or not The second column: tested or not

    Part 1

    [x] [ ] vsetivli     31=1 30=1 zimm10    zimm 14..12=0x7 rd 6..0=0x57
    [x] [ ] vsetvli      31=0 zimm11          rs1 14..12=0x7 rd 6..0=0x57
    [x] [ ] vsetvl       31=1 30..25=0x0 rs2  rs1 14..12=0x7 rd 6..0=0x57
    
    [x] [ ] vlm.v          31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0  vd 6..0=0x07
    [x] [ ] vsm.v          31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27
    
    [x] [ ] vle8.v         nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0  vd 6..0=0x07
    [x] [ ] vle16.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5  vd 6..0=0x07
    [x] [ ] vle32.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6  vd 6..0=0x07
    [x] [ ] vle64.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7  vd 6..0=0x07
    [x] [ ] vle128.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0  vd 6..0=0x07
    [x] [ ] vle256.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5  vd 6..0=0x07
    [x] [ ] vle512.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6  vd 6..0=0x07
    [x] [ ] vle1024.v      nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7  vd 6..0=0x07
    [x] [ ] vse8.v         nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27
    [x] [ ] vse16.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27
    [x] [ ] vse32.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27
    [x] [ ] vse64.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27
    [x] [ ] vse128.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27
    [x] [ ] vse256.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27
    [x] [ ] vse512.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27
    [x] [ ] vse1024.v      nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27
    
    [x] [x] vadd.vv        31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [x] vadd.vx        31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [x] vadd.vi        31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [x] vsub.vv         31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vsub.vx        31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vrsub.vx       31..26=0x03 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vrsub.vi       31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    
    [x] [x] vwaddu.vv      31..26=0x30 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vwaddu.vx      31..26=0x30 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vwsubu.vv      31..26=0x32 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwsubu.vx      31..26=0x32 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vwadd.vv       31..26=0x31 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwadd.vx       31..26=0x31 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vwsub.vv       31..26=0x33 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwsub.vx       31..26=0x33 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [x] vwaddu.wv      31..26=0x34 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vwaddu.wx      31..26=0x34 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vwsubu.wv      31..26=0x36 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwsubu.wx      31..26=0x36 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vwadd.wv       31..26=0x35 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwadd.wx       31..26=0x35 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vwsub.wv       31..26=0x37 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwsub.wx       31..26=0x37 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    
    [x] [ ] vzext.vf8      31..26=0x12 vm vs2 19..15=2 14..12=0x2 vd 6..0=0x57
    [x] [ ] vsext.vf8      31..26=0x12 vm vs2 19..15=3 14..12=0x2 vd 6..0=0x57
    [x] [ ] vzext.vf4      31..26=0x12 vm vs2 19..15=4 14..12=0x2 vd 6..0=0x57
    [x] [ ] vsext.vf4      31..26=0x12 vm vs2 19..15=5 14..12=0x2 vd 6..0=0x57
    [x] [x] vzext.vf2      31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57
    [x] [ ] vsext.vf2      31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57
    
    [x] [x] vadc.vvm       31..26=0x10 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vadc.vxm       31..26=0x10 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vadc.vim       31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vmadc.vvm      31..26=0x11 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmadc.vxm      31..26=0x11 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmadc.vim      31..26=0x11 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vmadc.vv       31..26=0x11 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmadc.vx       31..26=0x11 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmadc.vi       31..26=0x11 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57
    
    [x] [ ] vsbc.vvm       31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vsbc.vxm       31..26=0x12 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmsbc.vvm      31..26=0x13 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmsbc.vxm      31..26=0x13 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmsbc.vv       31..26=0x13 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmsbc.vx       31..26=0x13 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57
    
    [x] [ ] vand.vv         31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vand.vi        31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vand.vx        31..26=0x09 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vor.vv          31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vor.vx         31..26=0x0a vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vor.vi         31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vxor.vv         31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vxor.vx        31..26=0x0b vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vxor.vi        31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    
    [x] [ ] vsll.vv        31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vsll.vx        31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [x] vsll.vi        31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vsrl.vv        31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vsrl.vx        31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vsrl.vi        31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vsra.vv        31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vsra.vx        31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vsra.vi        31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    
    [x] [x] vnsrl.wv       31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [x] vnsrl.wx       31..26=0x2c vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vnsrl.wi       31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [x] vnsra.wv       31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [x] vnsra.wx       31..26=0x2d vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vnsra.wi       31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    
    [x] [x] vmseq.vv       31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [x] vmseq.vx       31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [x] vmseq.vi       31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vmsne.vv       31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmsne.vx       31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmsne.vi       31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vmsltu.vv      31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmsltu.vx      31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmslt.vv       31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmslt.vx       31..26=0x1b vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [x] vmsleu.vv      31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmsleu.vx      31..26=0x1c vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmsleu.vi      31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vmsle.vv       31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmsle.vx       31..26=0x1d vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmsle.vi       31..26=0x1d vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vmsgtu.vx      31..26=0x1e vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmsgtu.vi      31..26=0x1e vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vmsgt.vx       31..26=0x1f vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmsgt.vi       31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    
    [x] [ ] vminu.vv       31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vminu.vx       31..26=0x04 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmin.vv        31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmin.vx        31..26=0x05 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmaxu.vv       31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmaxu.vx       31..26=0x06 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmax.vv        31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmax.vx        31..26=0x07 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    
    [x] [x] vmul.vv        31..26=0x25 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vmul.vx        31..26=0x25 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vmulh.vv       31..26=0x27 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vmulh.vx       31..26=0x27 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vmulhu.vv      31..26=0x24 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vmulhu.vx      31..26=0x24 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vmulhsu.vv     31..26=0x26 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vmulhsu.vx     31..26=0x26 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    
    [x] [ ] vdivu.vv       31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vdivu.vx       31..26=0x20 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vdiv.vv        31..26=0x21 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vdiv.vx        31..26=0x21 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vremu.vv       31..26=0x22 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vremu.vx       31..26=0x22 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vrem.vv        31..26=0x23 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vrem.vx        31..26=0x23 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    
    [x] [x] vwmulu.vv      31..26=0x38 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwmulu.vx      31..26=0x38 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vwmulsu.vv     31..26=0x3a vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwmulsu.vx     31..26=0x3a vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vwmul.vv       31..26=0x3b vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwmul.vx       31..26=0x3b vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    
    [x] [x] vmv.v.v        31..26=0x17 25=1 24..20=0 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmv.v.x        31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmv.v.i        31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57
    
    [x] [ ] vsaddu.vv      31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vsaddu.vx      31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vsaddu.vi      31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vsadd.vv       31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vsadd.vx       31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vsadd.vi       31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vssubu.vv      31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vssubu.vx      31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vssub.vv       31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vssub.vx       31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    
    [x] [x] vaaddu.vv      31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vaaddu.vx      31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [x] vaadd.vv       31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vaadd.vx       31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [x] vasubu.vv      31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vasubu.vx      31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [x] vasub.vv       31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vasub.vx       31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    
    [x] [x] vfirst.m       31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57
    
    [x] [ ] vmv1r.v        31..26=0x27 25=1 vs2 19..15=0 14..12=0x3 vd 6..0=0x57
    [x] [ ] vmv2r.v        31..26=0x27 25=1 vs2 19..15=1 14..12=0x3 vd 6..0=0x57
    [x] [ ] vmv4r.v        31..26=0x27 25=1 vs2 19..15=3 14..12=0x3 vd 6..0=0x57
    [x] [ ] vmv8r.v        31..26=0x27 25=1 vs2 19..15=7 14..12=0x3 vd 6..0=0x57
    

    Part 2

    [x] [ ] vlse8.v         nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0  vd 6..0=0x07
    [x] [ ] vlse16.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5  vd 6..0=0x07
    [x] [ ] vlse32.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6  vd 6..0=0x07
    [x] [ ] vlse64.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7  vd 6..0=0x07
    [x] [ ] vlse128.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0  vd 6..0=0x07
    [x] [ ] vlse256.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5  vd 6..0=0x07
    [x] [ ] vlse512.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6  vd 6..0=0x07
    [x] [ ] vlse1024.v      nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7  vd 6..0=0x07
    
    [x] [ ] vsse8.v         nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27
    [x] [ ] vsse16.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27
    [x] [ ] vsse32.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27
    [x] [ ] vsse64.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27
    [x] [ ] vsse128.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27
    [x] [ ] vsse256.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27
    [x] [ ] vsse512.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27
    [x] [ ] vsse1024.v      nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27
    
    [x] [ ] vluxei8.v      nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0  vd 6..0=0x07
    [x] [ ] vluxei16.v     nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5  vd 6..0=0x07
    [x] [ ] vluxei32.v     nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6  vd 6..0=0x07
    [x] [ ] vluxei64.v     nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7  vd 6..0=0x07
    [x] [ ] vluxei128.v    nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0  vd 6..0=0x07
    [x] [ ] vluxei256.v    nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5  vd 6..0=0x07
    [x] [ ] vluxei512.v    nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6  vd 6..0=0x07
    [x] [ ] vluxei1024.v   nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7  vd 6..0=0x07
    
    [x] [ ] vsuxei8.v      nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
    [x] [ ] vsuxei16.v     nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
    [x] [ ] vsuxei32.v     nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
    [x] [ ] vsuxei64.v     nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
    [x] [ ] vsuxei128.v    nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
    [x] [ ] vsuxei256.v    nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
    [x] [ ] vsuxei512.v    nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
    [x] [ ] vsuxei1024.v   nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
    
    [x] [ ] vloxei8.v        nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0  vd 6..0=0x07
    [x] [ ] vloxei16.v       nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5  vd 6..0=0x07
    [x] [ ] vloxei32.v       nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6  vd 6..0=0x07
    [x] [ ] vloxei64.v       nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7  vd 6..0=0x07
    [x] [ ] vloxei128.v      nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0  vd 6..0=0x07
    [x] [ ] vloxei256.v      nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5  vd 6..0=0x07
    [x] [ ] vloxei512.v      nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6  vd 6..0=0x07
    [x] [ ] vloxei1024.v     nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7  vd 6..0=0x07
    
    [x] [ ] vsoxei8.v        nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
    [x] [ ] vsoxei16.v       nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
    [x] [ ] vsoxei32.v       nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
    [x] [ ] vsoxei64.v       nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
    [x] [ ] vsoxei128.v      nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
    [x] [ ] vsoxei256.v      nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
    [x] [ ] vsoxei512.v      nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
    [x] [ ] vsoxei1024.v     nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
    
    [x] [ ] vl1re8.v       31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd  6..0=0x07
    [x] [ ] vl1re16.v      31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd  6..0=0x07
    [x] [ ] vl1re32.v      31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd  6..0=0x07
    [x] [ ] vl1re64.v      31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd  6..0=0x07
    [x] [ ] vl2re8.v       31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd  6..0=0x07
    [x] [ ] vl2re16.v      31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd  6..0=0x07
    [x] [ ] vl2re32.v      31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd  6..0=0x07
    [x] [ ] vl2re64.v      31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd  6..0=0x07
    [x] [ ] vl4re8.v       31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd  6..0=0x07
    [x] [ ] vl4re16.v      31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd  6..0=0x07
    [x] [ ] vl4re32.v      31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd  6..0=0x07
    [x] [ ] vl4re64.v      31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd  6..0=0x07
    [x] [ ] vl8re8.v       31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd  6..0=0x07
    [x] [ ] vl8re16.v      31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd  6..0=0x07
    [x] [ ] vl8re32.v      31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd  6..0=0x07
    [x] [ ] vl8re64.v      31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd  6..0=0x07
    
    [x] [ ] vs1r.v         31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27
    [x] [ ] vs2r.v         31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27
    [x] [ ] vs4r.v         31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27
    [x] [ ] vs8r.v         31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27
    
    [x] [x] vmacc.vv       31..26=0x2d vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vmacc.vx       31..26=0x2d vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vnmsac.vv      31..26=0x2f vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vnmsac.vx      31..26=0x2f vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vmadd.vv       31..26=0x29 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vmadd.vx       31..26=0x29 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vnmsub.vv      31..26=0x2b vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vnmsub.vx      31..26=0x2b vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    
    [x] [x] vwmaccu.vv     31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwmaccu.vx     31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vwmacc.vv      31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwmacc.vx      31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vwmaccsu.vv    31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [ ] vwmaccsu.vx    31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [ ] vwmaccus.vx    31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    
    [x] [x] vmerge.vvm     31..26=0x17 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vmerge.vxm     31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vmerge.vim     31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57
    
    [x] [ ] vsmul.vv       31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vsmul.vx       31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    
    [x] [ ] vssrl.vx       31..26=0x2a vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vssrl.vv       31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vssrl.vi       31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vssra.vv       31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vssra.vx       31..26=0x2b vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vssra.vi       31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    
    [x] [ ] vnclipu.wv     31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vnclipu.wx     31..26=0x2e vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vnclipu.wi     31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [ ] vnclip.wv      31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vnclip.wx      31..26=0x2f vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [ ] vnclip.wi      31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    
    [x] [x] vredsum.vs     31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vredand.vs     31..26=0x01 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vredor.vs      31..26=0x02 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vredxor.vs     31..26=0x03 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vredminu.vs    31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vredmin.vs     31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vredmaxu.vs    31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vredmax.vs     31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vwredsumu.vs   31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [x] vwredsum.vs    31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    
    [x] [x] vmand.mm       31..26=0x19 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vmnand.mm      31..26=0x1d vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vmandnot.mm    31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vmxor.mm       31..26=0x1b vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vmor.mm        31..26=0x1a vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vmnor.mm       31..26=0x1e vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vmornot.mm     31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vmxnor.mm      31..26=0x1f vm vs2 vs1 14..12=0x2 vd 6..0=0x57
    
    [x] [x] vcpop.m        31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57
    [x] [x] vmsbf.m        31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57
    [x] [x] vmsof.m        31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57
    [x] [x] vmsif.m        31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57
    [x] [x] viota.m        31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57
    [x] [x] vid.v          31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57
    [x] [x] vmv.x.s        31..26=0x10 25=1 vs2 19..15=0 14..12=0x2 rd 6..0=0x57
    [x] [x] vmv.s.x        31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57
    [x] [x] vcompress.vm   31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57
    [x] [x] vslide1up.vx   31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [x] vslideup.vx    31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [x] vslideup.vi    31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [x] vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57
    [x] [x] vslidedown.vx  31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [x] vslidedown.vi  31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    [x] [x] vrgather.vx    31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57
    [x] [x] vrgather.vv     31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [x] vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57
    [x] [ ] vrgather.vi    31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57
    

    Part 3

    [ ] [ ] vle8ff.v         nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0  vd 6..0=0x07
    [ ] [ ] vle16ff.v        nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5  vd 6..0=0x07
    [ ] [ ] vle32ff.v        nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6  vd 6..0=0x07
    [ ] [ ] vle64ff.v        nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7  vd 6..0=0x07
    [ ] [ ] vle128ff.v       nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0  vd 6..0=0x07
    [ ] [ ] vle256ff.v       nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5  vd 6..0=0x07
    [ ] [ ] vle512ff.v       nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6  vd 6..0=0x07
    [ ] [ ] vle1024ff.v      nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7  vd 6..0=0x07
    
    [ ] [ ] vfadd.vf        31..26=0x00 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfsub.vf        31..26=0x02 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfmin.vf        31..26=0x04 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfmax.vf        31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfsgnj.vf       31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfsgnjn.vf      31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfsgnjx.vf      31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfslide1up.vf   31..26=0x0e vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfslide1down.vf 31..26=0x0f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfmv.s.f        31..26=0x10 25=1 24..20=0 rs1      14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfmerge.vfm    31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfmv.v.f       31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vmfeq.vf       31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vmfle.vf       31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vmflt.vf       31..26=0x1b vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vmfne.vf       31..26=0x1c vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vmfgt.vf       31..26=0x1d vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vmfge.vf       31..26=0x1f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfdiv.vf       31..26=0x20 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfrdiv.vf      31..26=0x21 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfmul.vf       31..26=0x24 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfrsub.vf      31..26=0x27 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfmadd.vf      31..26=0x28 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfnmadd.vf     31..26=0x29 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfmsub.vf      31..26=0x2a vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfnmsub.vf     31..26=0x2b vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfmacc.vf      31..26=0x2c vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfnmacc.vf     31..26=0x2d vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfmsac.vf      31..26=0x2e vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfnmsac.vf     31..26=0x2f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfwadd.vf      31..26=0x30 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfwsub.vf      31..26=0x32 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfwadd.wf      31..26=0x34 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfwsub.wf      31..26=0x36 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfwmul.vf      31..26=0x38 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfwmacc.vf     31..26=0x3c vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfwnmacc.vf    31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfwmsac.vf     31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfwnmsac.vf    31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
    [ ] [ ] vfadd.vv       31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfredusum.vs   31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfsub.vv       31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfredosum.vs   31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfmin.vv       31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfredmin.vs    31..26=0x05 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfmax.vv       31..26=0x06 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfredmax.vs    31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfsgnj.vv      31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfsgnjn.vv     31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfsgnjx.vv     31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfmv.f.s       31..26=0x10 25=1 vs2      19..15=0 14..12=0x1 rd 6..0=0x57
    [ ] [ ] vmfeq.vv       31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vmfle.vv       31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vmflt.vv       31..26=0x1b vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vmfne.vv       31..26=0x1c vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfdiv.vv       31..26=0x20 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfmul.vv       31..26=0x24 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfmadd.vv      31..26=0x28 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfnmadd.vv     31..26=0x29 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfmsub.vv      31..26=0x2a vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfnmsub.vv     31..26=0x2b vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfmacc.vv      31..26=0x2c vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfnmacc.vv     31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfmsac.vv      31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfnmsac.vv     31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfcvt.xu.f.v     31..26=0x12 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfcvt.x.f.v      31..26=0x12 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfcvt.f.xu.v     31..26=0x12 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfcvt.f.x.v      31..26=0x12 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfcvt.rtz.x.f.v  31..26=0x12 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwcvt.xu.f.v     31..26=0x12 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwcvt.x.f.v      31..26=0x12 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwcvt.f.xu.v     31..26=0x12 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwcvt.f.x.v      31..26=0x12 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwcvt.f.f.v      31..26=0x12 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwcvt.rtz.x.f.v  31..26=0x12 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfncvt.xu.f.w     31..26=0x12 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfncvt.x.f.w      31..26=0x12 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfncvt.f.xu.w     31..26=0x12 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfncvt.f.x.w      31..26=0x12 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfncvt.f.f.w      31..26=0x12 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfncvt.rod.f.f.w  31..26=0x12 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfncvt.rtz.x.f.w  31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfsqrt.v       31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfrsqrt7.v     31..26=0x13 vm vs2 19..15=0x04 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfrec7.v       31..26=0x13 vm vs2 19..15=0x05 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfclass.v      31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwadd.vv      31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwredusum.vs  31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwsub.vv      31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwredosum.vs  31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwadd.wv      31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwsub.wv      31..26=0x36 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwmul.vv      31..26=0x38 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwmacc.vv     31..26=0x3c vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwnmacc.vv    31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwmsac.vv     31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    [ ] [ ] vfwnmsac.vv    31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57
    
    [ ] [ ] vamoswapei8.v  31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
    [ ] [ ] vamoaddei8.v   31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
    [ ] [ ] vamoxorei8.v   31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
    [ ] [ ] vamoandei8.v   31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
    [ ] [ ] vamoorei8.v    31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
    [ ] [ ] vamominei8.v   31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
    [ ] [ ] vamomaxei8.v   31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
    [ ] [ ] vamominuei8.v  31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
    [ ] [ ] vamomaxuei8.v  31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
    [ ] [ ] vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
    [ ] [ ] vamoaddei16.v  31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
    [ ] [ ] vamoxorei16.v  31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
    [ ] [ ] vamoandei16.v  31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
    [ ] [ ] vamoorei16.v   31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
    [ ] [ ] vamominei16.v  31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
    [ ] [ ] vamomaxei16.v  31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
    [ ] [ ] vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
    [ ] [ ] vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
    [ ] [ ] vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
    [ ] [ ] vamoaddei32.v  31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
    [ ] [ ] vamoxorei32.v  31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
    [ ] [ ] vamoandei32.v  31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
    [ ] [ ] vamoorei32.v   31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
    [ ] [ ] vamominei32.v  31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
    [ ] [ ] vamomaxei32.v  31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
    [ ] [ ] vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
    [ ] [ ] vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
    [ ] [ ] vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
    [ ] [ ] vamoaddei64.v  31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
    [ ] [ ] vamoxorei64.v  31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
    [ ] [ ] vamoandei64.v  31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
    [ ] [ ] vamoorei64.v   31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
    [ ] [ ] vamominei64.v  31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
    [ ] [ ] vamomaxei64.v  31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
    [ ] [ ] vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
    [ ] [ ] vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
    
    opened by mohanson 1
  • Support A extension

    Support A extension

    We can implement the A extension on ckb-vm: considering that some Rust codes may use atomic operations, and rust only provides riscv64imac-unknown-none-elf target.

    $ rustup target list | grep riscv
    riscv32i-unknown-none-elf
    riscv32imac-unknown-none-elf
    riscv32imc-unknown-none-elf
    riscv64gc-unknown-linux-gnu
    riscv64gc-unknown-none-elf
    riscv64imac-unknown-none-elf
    
    opened by mohanson 0
  • USDT Probes on ckb-vm AsmMachine

    USDT Probes on ckb-vm AsmMachine

    • https://www.brendangregg.com/blog/2014-09-17/node-flame-graphs-on-linux.html
    • https://github.com/sthima/node-usdt
    • https://leezhenghui.github.io/linux/2019/03/05/exploring-usdt-on-linux.html
    opened by mohanson 0
  • Formally Verify CKB-VM via Sail

    Formally Verify CKB-VM via Sail

    Sail is a language for describing the instruction-set architecture (ISA) semantics of processors. The formal specification of RISC-V ISA is defined exactly in sail.

    We could leverage sail to compile x86 and RISC-V models both down to Coq definitions. From there we can formally prove that our x86 assembly implementation of each RISC-V instruction, fully confronts to the RISC-V official specification.

    Later when an aarch64 implementation is introduced, we could leverage the same proving techniques here.

    This solution has the issue that Rust based interpreter cannot be proved. But once we have a formally proved assembly based fast implementation, not so many will care about Rust based interpreter :P

    opened by xxuejie 0
Releases(v0.21.6)
  • v0.21.6(Sep 9, 2022)

    Summary

    Some small changes that will not have side effects on usage.

    ChangeLogs

    • fix: Stype display bug for branch instructions (https://github.com/nervosnetwork/ckb-vm/pull/281) @xxuejie
    • chore: Make fill_page_data a public function (https://github.com/nervosnetwork/ckb-vm/pull/287) @xxuejie
    • feat: Replace LD_SIGN_EXTENDED_32_CONSTANT with CUSTOM_LOAD_UIMM (https://github.com/nervosnetwork/ckb-vm/pull/288) @xxuejie
    Source code(tar.gz)
    Source code(zip)
  • v0.21.5(Aug 11, 2022)

  • v0.21.4(Aug 4, 2022)

    Greatly improve the performance of ckb-vm. When run ./ckb replay --tmp-target tmp --profile 7000000 7100000 in mainnet,

    • ckb v0.103.0 took 47 hours 30 minutes
    • ckb v0.103.0 with new ckb-vm only took 25 hours and 15 minutes

    ChangeLogs:

    • Calculate trace slot by shift 2 @XuJiandong @mohanson https://github.com/nervosnetwork/ckb-vm/pull/271
    Source code(tar.gz)
    Source code(zip)
  • v0.21.3(Jun 2, 2022)

    • Cosmetic enhancements. Optimize the print format of instructions to make them more human readable. #264 @xxuejie
    • Add a new feature named pprof to help ckb-debugger handle exec syscall #263 @mohanson
    Source code(tar.gz)
    Source code(zip)
  • v0.21.2(Apr 8, 2022)

  • 0.21.1(Dec 31, 2021)

    • Fix: Use valid assembly separator on Apple Silicon, ckb-vm can run correctly on macOS m1 now. @xxuejie
    • Refactor: Splitting out sub errors from OutOfBounds, InvalidPermission.. e.g. @mohanson
    Source code(tar.gz)
    Source code(zip)
  • 0.21.0(Dec 15, 2021)

  • 0.20.1(Nov 15, 2021)

  • 0.20.0(Nov 5, 2021)

  • 0.20.0-rc6(Oct 9, 2021)

  • 0.20.0-rc4(Aug 23, 2021)

  • 0.20.0-rc3(Aug 9, 2021)

  • 0.20.0-rc2(Jul 28, 2021)

    This update includes:

    • Return a unique error when cycles overflow #178 @mohanson
    • perf: add decoder instructions cache #180 @quake
    • Fix instruction length setting in asm's step() #181 @mohanson
    Source code(tar.gz)
    Source code(zip)
  • 0.20.0-rc1(Jul 6, 2021)

  • 0.20.0-alpha2(Jun 17, 2021)

    • Machine.reset() correctly set cycles and max_cycles now
    • Refactor: remove constructor Machine::default() and Machine::latest()
    • Add MOP instructions adc and sbb
    Source code(tar.gz)
    Source code(zip)
  • 0.20.0-alpha(May 20, 2021)

  • 0.19.4(May 7, 2021)

  • 0.19.3(Dec 4, 2020)

  • 0.19.2(Oct 10, 2020)

  • 0.19.1(Mar 4, 2020)

  • 0.19.0(Feb 4, 2020)

  • 0.18.2(Dec 18, 2019)

    This release contains the following changes:

    • #94 feat: Try scoop instead of chocolatey, besides CI changes, this also updates build configuration to make it compatible with yasm 1.3
    Source code(tar.gz)
    Source code(zip)
  • 0.18.1(Nov 30, 2019)

  • 0.18.0(Oct 17, 2019)

    This release contains the following changes:

    • #88: Expose running methods in SupportMachine trait
    • #89: Implement StdError for Error @brson
    Source code(tar.gz)
    Source code(zip)
  • 0.17.0(Sep 25, 2019)

  • 0.16.0(Sep 10, 2019)

    This release contains the following changes:

    • #80 Fix ELF parsing panics in AOT mode
    • #81 Upgrade goblin @driftluo
    • #82 Fix FlatMemory overflowing bug
    • #83 Add EBREAK support for debugger integration
    • #84 Add Windows support for assembly interpreter via YASM
    Source code(tar.gz)
    Source code(zip)
  • 0.15.1(Jul 27, 2019)

  • 0.15.0(Jul 27, 2019)

    This is an important release. We are adding a brand new AOT mode for executing CKB VM programs with huge speedup.

    Specifically, this release contains the following changes:

    • #68 Replace uses of rounddown / roundup with round_page_down / round_page_up @brson
    • #71 Eliminate as much usize as making sense from CKB VM
    • #72 feat: Add new AOT mode to replace experimental JIT mode
    • #74 feat: Do not trigger coverage jobs in PRs
    • #75 test: avoid make-cov run test two times @u2
    • #76 feat: Set codecov coverage target
    • #77 feat: Add benchmarks for ASM & AOT VM
    • #78 fix: Various places where panic might happen in case of malicious data
    • #79 chore: update rust to 1.36.0 @u2
    Source code(tar.gz)
    Source code(zip)
  • v0.14.0(Jun 10, 2019)

    This release contains the following changes:

    • #67 Replace custom power_of_2 function with std @brson
    • #69 Add flag denoting if PC should be updated when loading ELF. Note: this is a breaking change since a public API is changed
    • #70 Add coverage CI job containing full CKB VM test suite
    Source code(tar.gz)
    Source code(zip)
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