RISC-V instruction decoder written in Rust.

Related tags

Miscellaneous decoder risc-v
Overview

raki

Rust
RISC-V instruction decoder written in Rust.

  • Both 32/64bit support.
  • Support rv32/64imac, Zicsr, Zifencei extensions.
  • Implement Display trait for formatting.

Usage

Call the decode as u16/u32 method.

use raki::Isa;
use raki::decode::Decode;
use raki::instruction::Instruction;

let inst: u32 = 0b1110_1110_1100_0010_1000_0010_1001_0011;
let inst: Instruction = match inst.decode(Isa::Rv32) {
    Ok(inst) => inst,
    Err(e) => panic!("decoding failed due to {e:?}"),
};
println!("{inst}");
// --output--
// addi t0, t0, -276

License

This crate is licensed under MIT.
See LICENSE for details.

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Comments
  • Ver 0.1.2

    Ver 0.1.2

    • Fix zicsr decoding.
    • Modify to fllow the compressed format in official specification.
    • Fix c.jr and c.addi16sp to get rd value.
    • Rename Xtype to Xformat in InstFormat.
    • Add Tag workflow.
    opened by Alignof 0
  • Support 'Q' Extension

    Support 'Q' Extension

    Support 'Q' Standard Extension for Quad-Precision Floating-Point.

    • [ ] RV32Q Standard Extension
    • [ ] RV64Q Standard Extension
    • [ ] Floating point register
    enhancement 
    opened by Alignof 0
  • Support 'D' extension

    Support 'D' extension

    Support 'D' Standard Extension for Double-Precision Floating-Point.

    • [ ] RV32D Standard Extension
    • [ ] RV64D Standard Extension
    • [ ] RV32/64DC Extension
    • [ ] Floating point register
    enhancement 
    opened by Alignof 0
  • Support 'F' extension

    Support 'F' extension

    Support 'F' Standard Extension for Single-Precision Floating-Point.

    • [ ] RV32F Standard Extension
    • [ ] RV64F Standard Extension
    • [ ] Floating point instruction in C Extension
    • [ ] Floating point register
    enhancement 
    opened by Alignof 0
Releases(v0.1.3)
Owner
Norimasa Takana
dokidoki visual engineer
Norimasa Takana
GitHub https://crates.io/crates/raki
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