Veryl: A Modern Hardware Description Language

Overview

Veryl

Veryl is a modern hardware description language.

This project is under the exploration phase of language design. If you have any idea, please open Issue.

Actions Status Crates.io Changelog

Documentation quick links

Concepts

Veryl is designed as a "SystemVerilog Alternative". There are some design concepts.

Symplified Syntax

Veryl has symplified syntax based on SystemVerilog / Rust. "Symplified" has two meanings. One is for parser, and another is for human.

SystemVerilog has very complicated syntax (see IEEE Std 1800-2017 Annex A). This causes difficulty of SystemVerilog tool implementation. So Veryl should have simple syntax to parse. For example, "off-side rule" like Python, "automatic semicolon insertion" like ECMAScript / Go will not be supported.

SystemVerilog has various syntax. Some syntaxes are inherited from Verilog, and some syntaxes are added from SystemVerilog. Additionally some syntaxes can be written, but cannot be used actually because major EDA tools don't support them. So user should learn many syntaxes and whether each syntax can be used or not. Veryl will not support old Verilog style, unrecommended description, and so on.

Transpiler to SystemVerilog

HDL alternative languages should be transpiler to the tradisional HDLs like Verilog / VHDL because major EDA tools support them. Veryl is a transpiler to SystemVerilog.

Transpiler to Verilog has wide EDA tool support including OSS EDA tools. But even if there are rich data strucuture like struct / interface in HDL alternatives, transpiled Verilog can't have it. If HDL alternatives have rich code generateion mechanism, transpiled Verilog will be expanded to the very long code. For these reason, debugging the transpiled code becomes difficult.

Veryl will has almost all the same semantics as SystemVerilog. So transpiled code will be human readable SystemVerilog.

Additionally Veryl have interoperability with SystemVerilog. Veryl can use SystemVerilog's module / interface / struct / enum in the code, and vice versa.

Integrated Tools

Modern programming languages have development support tools like linter, formatter, and language server by default. Veryl will have them too from the beginning of development.

The following tools are planed to support.

  • Semantic checker
  • Source code formatter
  • Language server
  • Package manager

Installation

Download binary

Download from release page, and extract to the directory in PATH.

Cargo

You can install with cargo.

cargo install veryl veryl-ls

Usage

  • Create a new package
veryl new [package name]
  • Create a new package in an existing directory
veryl init [path]
  • Format the current package
veryl fmt
  • Analyze the current package
veryl check
  • Build target codes corresponding to the current package
veryl build

Examples

Source Code

Veryl: https://github.com/dalance/veryl/tree/master/testcases/vl

Transpiled SystemVerilog: https://github.com/dalance/veryl/tree/master/testcases/sv

Package Configuration

[package]
name = "name"      # package name
version = "0.1.0"  # package version (semver is recommended)

[build]
clock_type = "posedge"    # default clock type [posedge|negedge]
reset_type = "async_low"  # default reset type [async_low|async_high|sync_low|sync_high]

# output target files in the same location as source
target     = {type = "source"}

# output target files in the specified directory
#target     = {type = "directory", path = "testcases/sv"}

[format]
indent_width = 4  # indent width

Reference

License

Licensed under either of

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Comments
  • Loop statement support

    Loop statement support

    My existing SV code includes loop statements such as for loop and while loop so I'd like Veryl to support these statements.

    I think SV (C lang) style for loop statement is very bother notation because there are many similar code for example int i = 0; and ++i;. So I'd like you to introduce simple notation.

    lang 
    opened by taichi-ishitani 5
  • Not report a syntax error when parsing VL code including syntax error

    Not report a syntax error when parsing VL code including syntax error

    I got a problem that veryl build command does not report a error when parsing VL code including a syntax error.

    How to reproduce:

    Run veryl build command with following VL code.

    module test_module (
     i_clk: input logic,
     i_rst_n: input logic,
     i_d: input logic,
     o_d: output logic
    ) {
      d: logic;
    
      always_comb {
        o_d = d;
      }
    
      always_ff (i_clk, i_rst_n) {
        if_rest {
          d = 0;
        }
        else {
          d = i_d;
        }
      }
    }
    

    I expect the command reports a syntax error because there is a typo (if_reset -> if_rest). But the command completes SV code generation.

    bug 
    opened by taichi-ishitani 4
  • let / inst statement

    let / inst statement

    let statement for variable declaration and module/interface instantiation.

    // variable declaration
    let value_a: logic [10];
    
    // assignment after declaration
    assgin value_a = 1;
    
    // variable declaration with assignment
    let value_b: logic [10] = 1;
    
    // module instantiation
    let module_a: inst moduleA;
    
    // interface instantiation
    let if_a: inst interfaceA;
    
    // interface array
    let if_b: inst interfaceB [10];
    
    // module with parameter and port connection
    let module_b: inst moduleB #(
        a,
        b: 10,
    ) {
        a,
        b: 10,
    };
    
    
    
    lang 
    opened by dalance 4
  • Need to insert type cast

    Need to insert type cast

    Inserting type cast is needed when LHS of assignment is enum variable and RHS of assignment is non-enum value. If no type cast is inserted then EDA tool may report a warning like below.

    Warning-[ENUMASSIGN] Illegal assignment to enum variable
    testbench.sv, 13
    test, "foo_bar = 0;"
      Only expressions of the enum type can be assigned to an enum variable. 
      The type int is incompatible with the enum 'e_foo_bar'
      Expression: 0
      Use the static cast operator to convert the expression to enum type.
    

    However generated SV code does not include type cast.

    orignal VL code:

    module test {
      enum e_foo_bar: logic [1] {
        foo = 0,
        bar = 1
      }
    
      let foo_bar: e_foo_bar;
      always_comb {
        foo_bar = foo;
        foo_bar = bar;
        foo_bar = 0;
        foo_bar = 1;
      }
    }
    

    generated SV code:

    module test ;
        typedef enum logic [1-1:0] {
            foo = 0,
            bar = 1
        } e_foo_bar;
        e_foo_bar foo_bar ;
        always_comb begin
            foo_bar = foo;
            foo_bar = bar;
            foo_bar = 0;
            foo_bar = 1;
        end
    endmodule
    
    opened by taichi-ishitani 3
  • Generated SV code with comments is illegal

    Generated SV code with comments is illegal

    The build commmand genertes illegal SV code from VL code with comments. These comments are put:

    • between else and if of else-if statement
    • before condition of if statement

    These are an exaple code and generated SV code:

    module test_module (
     i_clk: 	input logic,
     i_rst_n:	input logic,
     i_up:	input logic,
     i_down:    input logic,
     o_count:	output logic[8]
    ) {
      count: 	logic[8];
      up_down: 	logic[2];
    
      always_comb {
        up_down = (i_up << 1) | i_down;
      }
    
      always_ff (i_clk, i_rst_n) {
        if_reset {
          count = 0;
        }
        else // count up
        if up_down == 2'b10 {
          count = count + 1;
        }
        else if // count down
        up_down == 2'b01 {
          count = count - 1;
        }
      }
    }
    
    module test_module (
        input  logic         i_clk  ,
        input  logic         i_rst_n,
        input  logic         i_up   ,
        input  logic         i_down ,
        output logic [8-1:0] o_count
    ) ;
        logic [8-1:0] count  ;
        logic [2-1:0] up_down;
        always_comb begin
            up_down = (i_up << 1) | i_down;
        end
        always_ff @ (posedge i_clk, negedge i_rst_n) begin
            if (!i_rst_n) begin
                count <= 0;
            end else // count up if (up_down == 2'b10) begin
                count <= count + 1;
            end else if // count down (up_down == 2'b01) begin
                count <= count - 1;
            end
        end
    endmodule
    

    if (up_down == 2'b10) begin and (up_down == 2'b01) begin are hidden because they are comments. I think /* */ comment format should be used for inserted comments.

    bug 
    opened by taichi-ishitani 3
  • Part select using position and width

    Part select using position and width

    Part select using position and width (a[pos+:WIDTH]/a[pos-:WIDTH]) is useful feature. So I'd like you to import this feature to veryl.

    In addition, I think part select using index and width like below is a code showing often.

    b = a[2*i+:2];
    

    Therefore, I'd like you to introduce a syntax sugger for this code like below.

    b = a[2, i]; // a[2*i+:2]
    
    lang 
    opened by taichi-ishitani 3
  • remove () in always_ff

    remove () in always_ff

    Removing () in always_ff is uniform as if statement.

    always_ff (clk) {
    }
    always_ff (clk, rst) {
    }
    always_ff (posedge clk, async_low rst) {
    }
    

    to

    always_ff clk {
    }
    always_ff clk, rst {
    }
    always_ff posedge clk, async_low rst {
    }
    
    lang 
    opened by dalance 3
  • Using SV sytem functions

    Using SV sytem functions

    SystemVerilog has useful sytem functions, such as $clog2. I'd like to use SV system functions within VL code but I got a syntax error.

    Error: parol_runtime::unexpected_token
    
      × Unexpected token: LA(1) (Error)
       ╭─[test.vl:3:1]
     3 │   parameter MAX_COUNT:   u32 = 8,
     4 │   parameter COUNT_WIDTH: u32 = $clog2(MAX_COUNT + 1)
       ·                                ┬
       ·                                ╰── Unexpected token
     5 │ )(
       ╰────
      help: Unexpected token
    

    Does not support such feature?

    lang 
    opened by taichi-ishitani 2
  • Bump parol_runtime from 0.9.0 to 0.10.0

    Bump parol_runtime from 0.9.0 to 0.10.0

    Bumps parol_runtime from 0.9.0 to 0.10.0.

    Changelog

    Sourced from parol_runtime's changelog.

    Change Log

    All notable changes to this project will be documented in this file.

    The format is based on Keep a Changelog and this project adheres to Semantic Versioning.

    Be aware that this project is still v0.y.z which means that anything can change anytime:

    "4. Major version zero (0.y.z) is for initial development. Anything MAY change at any time. The public API SHOULD NOT be considered stable."

    (Semantic Versioning Specification)

    Indicating incompatible changes on major version zero

    We defined for this project that while being on major version zero we mark incompatible changes with new minor version numbers. Please note that this is no version handling covered by Semver.

    Commits

    Dependabot compatibility score

    Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting @dependabot rebase.


    Dependabot commands and options

    You can trigger Dependabot actions by commenting on this PR:

    • @dependabot rebase will rebase this PR
    • @dependabot recreate will recreate this PR, overwriting any edits that have been made to it
    • @dependabot merge will merge this PR after your CI passes on it
    • @dependabot squash and merge will squash and merge this PR after your CI passes on it
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    dependencies 
    opened by dependabot[bot] 2
  • Bump parol_runtime from 0.9.0 to 0.11.0

    Bump parol_runtime from 0.9.0 to 0.11.0

    Bumps parol_runtime from 0.9.0 to 0.11.0.

    Changelog

    Sourced from parol_runtime's changelog.

    Change Log

    All notable changes to this project will be documented in this file.

    The format is based on Keep a Changelog and this project adheres to Semantic Versioning.

    Be aware that this project is still v0.y.z which means that anything can change anytime:

    "4. Major version zero (0.y.z) is for initial development. Anything MAY change at any time. The public API SHOULD NOT be considered stable."

    (Semantic Versioning Specification)

    Indicating incompatible changes on major version zero

    We defined for this project that while being on major version zero we mark incompatible changes with new minor version numbers. Please note that this is no version handling covered by Semver.

    Commits

    Dependabot compatibility score

    Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting @dependabot rebase.


    Dependabot commands and options

    You can trigger Dependabot actions by commenting on this PR:

    • @dependabot rebase will rebase this PR
    • @dependabot recreate will recreate this PR, overwriting any edits that have been made to it
    • @dependabot merge will merge this PR after your CI passes on it
    • @dependabot squash and merge will squash and merge this PR after your CI passes on it
    • @dependabot cancel merge will cancel a previously requested merge and block automerging
    • @dependabot reopen will reopen this PR if it is closed
    • @dependabot close will close this PR and stop Dependabot recreating it. You can achieve the same result by closing it manually
    • @dependabot ignore this major version will close this PR and stop Dependabot creating any more for this major version (unless you reopen the PR or upgrade to it yourself)
    • @dependabot ignore this minor version will close this PR and stop Dependabot creating any more for this minor version (unless you reopen the PR or upgrade to it yourself)
    • @dependabot ignore this dependency will close this PR and stop Dependabot creating any more for this dependency (unless you reopen the PR or upgrade to it yourself)
    dependencies 
    opened by dependabot[bot] 2
  • Bump parol from 0.14.0 to 0.15.1

    Bump parol from 0.14.0 to 0.15.1

    Bumps parol from 0.14.0 to 0.15.1.

    Commits

    Dependabot compatibility score

    Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting @dependabot rebase.


    Dependabot commands and options

    You can trigger Dependabot actions by commenting on this PR:

    • @dependabot rebase will rebase this PR
    • @dependabot recreate will recreate this PR, overwriting any edits that have been made to it
    • @dependabot merge will merge this PR after your CI passes on it
    • @dependabot squash and merge will squash and merge this PR after your CI passes on it
    • @dependabot cancel merge will cancel a previously requested merge and block automerging
    • @dependabot reopen will reopen this PR if it is closed
    • @dependabot close will close this PR and stop Dependabot recreating it. You can achieve the same result by closing it manually
    • @dependabot ignore this major version will close this PR and stop Dependabot creating any more for this major version (unless you reopen the PR or upgrade to it yourself)
    • @dependabot ignore this minor version will close this PR and stop Dependabot creating any more for this minor version (unless you reopen the PR or upgrade to it yourself)
    • @dependabot ignore this dependency will close this PR and stop Dependabot creating any more for this dependency (unless you reopen the PR or upgrade to it yourself)
    dependencies 
    opened by dependabot[bot] 1
  • concatenation

    concatenation

    Verilog style

    assign a = {x, 1'b1, y[10:0]};
    assign a = {{10{x}}, {10{y}}}; 
    

    Repeat style has some problems.

    • too many {}
    • parsing difficulty (concatenation can't detect until consuming expression of repeating number)

    To resolve the second, repeating number should be after repeating operator. Repeating operator should be keyword or symbol?

    assign = a { x repeat 10, y repeat 10};
    assign = a { x @ 10, y @ 10};
    
    lang 
    opened by dalance 1
  • modport at port declaration

    modport at port declaration

    Is adding modport in port declaration of module declaration more explicit?

    module ModuleA (
        a: input   logic,
        b: output  logic,
        c: modport InterfaceA.master,
    ) {
    }
    
    lang 
    opened by dalance 0
  • enum value range check

    enum value range check

    The veryl build command generates SV code even if an enum value is outrange.

    orignal VL code:

    module test {
      enum e_foo_bar: logic [1] {
        foo = 0,
        bar = 2
      }
    }
    

    generated SV code:

    module test ;
        typedef enum logic [1-1:0] {
            foo = 0,
            bar = 2
        } e_foo_bar;
    endmodule
    

    The verly command needs to check range of enum values because this causes a compile error.

    Error-[ENUMRANGE] Enum label outside value range
    testbench.sv, 7
      The enum label 'BAR' has the value 2 which is outside the range of the base 
      type of the enum 'e_foo_bar', which is 1 bit unsigned.
      If this is indeed the intended value, consider expressing it as as sized 
      literal of the same width and signedness as the enum base type.
    
    tools 
    opened by taichi-ishitani 3
  • allow variable forward reference

    allow variable forward reference

    SystemVerilog don't allow variable forward reference. It causes distributed variable declarations which are included in the same group.

    // Move the declaration to the top of code to avoid forward reference
    let b2: logic;
    
    // Module A
    let a0: logic = b2 + 1;
    
    // Module B
    let b0: logic;
    let b1: logic;
    // let b2: logic <- This position is suitable
    

    Unlike general programming language, RTL don't have code order. So variable forward reference is natural in RTL.

    lang 
    opened by dalance 0
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