DO processor

Related tags

System tools do-core1
Overview

do-core1

The do-core1 is a simple processor architecture, mostly for educational purposes.

It aims at being a support for system programming and computer architecture fundamentals courses.

Instruction Set Architecture

The do-core1 Instruction Set Architecture (ISA) is a simple Reduced Instruction Set Computer (RISC) processor architecture, with a very limited memory model and instruction and register set.

Registers

do-core1 exposes 8 general purpose registers: R0, R1, R2, R3, R4, R5, R6, R7.

It also uses one Instruction Pointer (RIP) register and a operation flags (RFLAGS) register.

All do-core1 registers are 16 bits wide.

Memory Model

do-core1 can address up to 4KiB (4096 bytes) of physical memory.

Instruction Set

do-core1 is a RISC architecture and executes fixed-length instructions of 16 bits.

The do-core1 is a 2-operand architecture, i.e. its instruction takes at most 2 operands. do-core1 operands are register indexes.

A do-core1 instruction can be split into an operation code (opcode), the first operand (op0) and the second operand (op1). The opcode is 8 bits long, and both operands are 4 bits long:

do-core instruction (16 bits)

Bits  |15                   8|7                4|3               0|
      -------------------------------------------------------------
      |  Opcode (bits 15-8)  |  op0 (bits 7-4)  | op1 (bits 3-0)  |
      -------------------------------------------------------------

The do-core1 is a load-store architecture and supports the following instructions:

Opcode Instruction Description
0x00 LD Rn, Rm Load the value at the memory address contained in Rm into Rn
0x01 ST Rn, Rm Store the value from Rn into the memory address contained in Rm
0x02 ADD Rn, Rm Add the value contained in Rm into Rn (Rn = Rn + Rm)
0x03 XOR Rn, Rm Perform a bitwise exclusive OR between Rn and Rm(Rn = Rn ^ Rm)
Comments
  • Architecture upgrade interrogation

    Architecture upgrade interrogation

    Hello!

    I'm currently working the implementation of the memory into do-core1. But I have some interrogation about how to do things as for now I have a fork where I'm trying to implement the memory.

    Firstly, I moved the whole process of instructions in a module Cpu, so we move away memory and cpu from main.rs. It might not be the best way to do that, can I have your mind on it ?

    Then, the Cpu module has now load and store OpCode, but as we discussed my understanding of these OpCode was wrong, as the register should store the address (which match with the index of Vector in my memory module) of the memory and not the value from memory. It is not fixed as I don't know how to handle this problem, must the register store literally the index of the address or a reference ?

    Thanks

    opened by AlexandreBrg 6
  • feat(#3): Derive FromStr for OpCode using strum dependency

    feat(#3): Derive FromStr for OpCode using strum dependency

    This will allow my assembler to depend on do-core for its OpCode parsing

    I added a dependency to strum and strum_macros to automatically generate the FromStr implementation, which doesn't introduce any overhead to adding new opcodes.

    opened by Hasenn 5
  • What does an instruction look like ?

    What does an instruction look like ?

    The Readme states the instructions are 32bit wide but still explains that " a do-core1 instruction can be split into an operation code (opcode), the first operand (op0) and the second operand (op1). The opcode is 6 bits long, and operands are 5 bits long:"

    So that would be 16 bit wide,

    Did we change the word size only or is the new instruction shape undocumented ?

    opened by Hasenn 2
  • Implement std::str::FromStr for OpCode

    Implement std::str::FromStr for OpCode

    As of now, in my assembler I need to redefine OpCode in order to derive that trait -- with strum's EnumString derive macro, which is a code duplication i can't really avoid. if the do-core crate did it, i could depend on it and not have to sync my assembler's instructions with do-core manually

    opened by Hasenn 1
  • Can special registers be instruction arguments

    Can special registers be instruction arguments

    Hi, I'm writing an assembler for do-core, i'm wondering wether special registers like RIP and RFLAGS can be arguments for instructions ? would things like these be possible:

    INC RIP 5
XOR R2 RFLAGS
    opened by Hasenn 1
  • feat CI: Add CI for stable version

    feat CI: Add CI for stable version

    This PR contains the necessary to run a simple CI job on our project.

    Actually the CI is configured to build the application with the stable toolchain, run all tests, run cargo clippy and cargo fmt.

    Missing behaviors:

    • Build the app with the nightly release
    • Build the app with the beta release
    opened by thomasgouveia 0
  • Feat: Logical feats & CLI

    Feat: Logical feats & CLI

    Added shift left and shift right operators, with tests. Application is panicking when overflowing or underflowing, it is intended.

    Decoding instruction from CLI by running cargo run -- --instruction 0x1842 for example. It is decoding the instruction properly, but it is not executing it yet.

    opened by lucido-simon 0
  • Missing instruction fetching

    Missing instruction fetching

    The Core crate decodes and executes instructions, but does not fetch instructions from memory.

    In order to fetch instructions, a core needs to know where the code is actually loaded in memory. This could be overwritten by the still missing executable format, but I propose that the default code section starts at 0x100 in memory. Unless overwritten, $RIP should be initially set to that value, and this is where the first instruction will live (a.k.a. as the reset vector).

    The fetch-decode-execute loop should then be as simple as:

    1. Read 32 bits from $RIP, that's the next instruction to decode and execute
    2. Increase RIP by 4 (next instruction, 32 bits further)
    3. Decode the instruction
    4. Execute the instruction
    5. goto step 1

    Note that the instruction executions step (step 4) could modify RIP as well (branches and jumps).

    opened by sameo 0
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