Introduction
This projects attempts to create a Rust-like hardware description language. Note that this has nothing to do with Rust itself, it just has a very similar syntax to Rust. At the moment this project is in it’s early planning and development stage.
How it should work
You write some Rust-like HDL and use the transpiler to turn it into (System-)Verilog.
Contributing
I mainly want your opinions on the syntax of this HDL. But code improvements are welcome too!
Syntax/Grammar
This is not the final syntax/grammar, it may change drastically! See ./transpiler/src/frontend/rustylog.pest
Examples
Accumulator (from llhd.io)
pub struct Accumulator {
pub clk: Input<Logic>,
pub direction: Input<Logic>,
pub increment: Input<[Logic; 16]>,
pub result: Output<[Logic; 16]>,
next: [Logic; 16],
}
impl Accumulator {
pub fn new(clk: Input<Logic>, direction: Input<Logic>, increment: Input<[Logic; 16]>, result: Output<[Logic; 16]>) -> Self {
Self {
clk,
direction,
increment,
result,
// TODO: next
}
}
#[always_comb]
fn increment(&mut self) {
if self.direction {
self.result = self.result + self.increment;
} else {
self.result = self.result - self.increment;
}
}
#[always_ff(clk: posedge)]
fn load_result(&mut self) {
self.result <= self.next;
}
}
pub struct Top {
acc: Accumulator,
}
impl Top {
pub fn new(clk: Input<Logic>, direction: Input<Logic>, increment: Input<[Logic; 16]>, result: Output<[Logic; 16]>) -> Top {
Self {
acc: Accumulator::new(clk, direction, increment, result),
}
}
}
Resources
TODOs
- type X = Y;
- Syntactic Sugar for State Machines
- Look into nom
- Integration with LLHD
- Look into Bluespec